Linux Multi Processor

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(Last revised: 2015-09-18)

Working with Linux Multi-Processors

What processors are on this machine?

You can list processors with

 $ cat /proc/cpuinfo

Each "processor" is a core of a processor. The login node, for instance, says it has eight Intel E5450 processors, and Intel Processorfinder says the E5450 are quad-core chips. If you look at /proc/cpuinfo in more detail, you can see the number of cores per CPU and whether hyper-threading is enabled. Here is a sample from the Linux login node:

processor 0 1 2 3 4 5 6 7
physical id 0 1 0 1 0 1 0 1
siblings 4 4 4 4 4 4 4 4
core id 0 0 2 2 1 1 3 3
cpu cores 4 4 4 4 4 4 4 4
  • processor - the logical processor index
  • physical id - which physical CPU contains this processor
  • siblings - the number of logical processors associated with the same physical CPU
  • core id - the index of the core on its CPU
  • cpu cores - the number of physical cores on this CPU

If siblings = 2*cpu cores, hyperthreading is on. You will find hyperthreading disabled on the CAC clusters.

Is the number of cores on a node important to your job script? Try

 $ nprocs=`grep processor /proc/cpuinfo | wc -l`

For the main cluster, it is possible we may add nodes with different processor speeds, so the processor identifier might change. The important parts, that you can compile code specifically for features of Intel Core2 architecture, should not change from node to node.

Can I limit an application to use fewer than the total number of cores?

Numactl says it controls non-uniform memory allocation (NUMA), but it also can specify which cores a program should use.

 $ numactl --physcpubind 0,3,6 myapp arg1 arg2

This specifies that myapp can run on only cores 0, 3, and 6. You can see how many cores are available using:

 $ numactl --show numactl
 policy: default
 preferred node: current
 physcpubind: 0 1 2 3 4 5 6 7
 cpubind: 0
 nodebind: 0
 membind: 0

The 0 in cpubind, nodebind, and membind refers to the first memory controller. This example was not run on a machine with non-uniform memory access, so there is only one memory controller. On an AMD chip or an Intel i7 architecture, you might see more listed.